The present disclosure relates to the fabrication of high performance field-effect transistors in CMOS integrated circuits, and more particularly, relates to methods for integrating and modulating the strain-induced process steps to enhance the transistors' performance.
Very large scale integrated (VLSI) circuits using field effect transistors (FET) experience problems with the strain or mechanical stress induced by the silicon and/or silicon-germanium substrate's lattice mismatch created by certain process steps during device fabrication. The strain induced upon the transistors' gate electrical channel affect the transistors' electrical field strength and carrier mobility performance. In complimentary metal oxide semiconductor (CMOS) devices, strain effect can be an especially difficult issue to deal with because the devices comprise of different transistor types. The affects of various strain magnitudes and strain directions upon a given transistor size and orientation have varying affects upon different transistor types. For example, tensile stress/strain applied in the direction parallel to the gate channel of an n-channel MOS transistor will provide improved drive current (Id) performance, while the same stress applied upon an identical sized and oriented p-channel transistor will cause degraded Id performance. As transistor geometric sizing and distances scale down, strain/stress affects applied upon the MOS transistors become relatively more strong and difficult to overcome.
Strain-inducing process operations are numerous in the fabrication flow of CMOS devices. One critical process loop for example, the shallow trench isolation (STI) fabrication, involves the construction of a substrate structure to isolate and define the transistors' active regions. The STI process loop of trench etching, trench filling, planarization and annealing results with a completed STI structure inducing stress onto the transistors from at least two axial (biaxial) directions. Processes that do not directly modify the substrate may also apply additional strain upon the transistor. Such processes create structures such as the sidewall spacers and contact etch stop (CES) layer, films that are deposited or grown on top of and/or adjacent to the transistor gates. Other strain inducing processes such as the metal silicidation processes involve the reaction of dissimilar materials to form new layers near the gate channel.
FIG. 1 illustrates a cross-sectional view of a conventional field-effect transistor 100 showing the basic components thereof with some of the above-mentioned strain inducing structures. The figure also has been labeled with three axis to show the three directions of how strain fields are applied with respect to the FET orientation. The substrate 101 area located between STI structures 102a and 102b is the defined transistor active region. The gate region comprising of a gate oxide 103 and gate electrode 104 is fabricated within this active region. Gate sidewall liners 105 and gate sidewall spacers 106a and 106b are situated adjacent to the gate region. The gate electrical channel shown as distance g is defined as the region of the substrate surface under the gate region, between the source (distance s) and drain (distance d) substrate regions of the transistor. The source s and drain d regions extend out from the ends of the gate channel to the STI structures. Metal-silicided electrodes areas are formed on top of the transistor's gate, source and drain regions. These regions are shown in FIG. 1 as gate silicide 107, source silicide 108 and drain silicide 109 regions. The contact etch stop (CES) 110 layer is shown, situated on top of the entire transistor at the process point just prior to the contact masking/patterning operations of the device.
The strain/stress forces are specified by the three dimensional axis x, y and z. For the discussions within the present disclosure, the axis parallel to the gate channel across the substrate along the direct path to and from the source and drain regions is known as the x direction, as shown in FIG. 1. The strain axis perpendicular to the gate channel across the substrate is known as the y direction. The third axis z is the strain direction directly normal to the substrate surface and to the plane created by axis x and y. It is noted that the various fabricated transistor structures shown in FIG. 1 will apply a variety of strain forces onto the transistor's gate channel in various magnitudes and directions. In the conventional CMOS technologies, the two-component x-y biaxial strain from the STI structures is a large portion of the net effect.
Accordingly, it is desirable to have a method for modulating the net strain induced by the various device fabrication processes/structures. An engineering and design method is desired for specifically modulating strain in certain preferential magnitudes and axial directions to allow for the simultaneous improvement of both NMOS and PMOS transistors.